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CS4970X4 Data Sheet
FEATURES
Multi-standard 32-bit High Definition Audio Decoding plus Post Processing Supports high-definition audio formats including: -- Dolby Digital(R) Plus -- Dolby(R) TrueHD -- DTS-HD
TM
32-bit High Definition Audio Decoder DSP Family with Dual DSP Engine Technology
Customer Software Security Keys 6 Channel DSD(R) Input 16 Ch x 32-bit PCM Out with Dual 192 kHz SPDIF Tx Two SPITM/I2C(R), One Parallel and One UART Port Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial Flash Memory Support
High Resolution Audio
-- DTS-HDTM Master Audio -- DSD(R) Additional Applications Library -- Dolby Digital(R) EX, Dolby(R) Pro Logic(R) IIx, Dolby Headphone(R), Dolby(R) Virtual Speaker(R) -- DTS-ES 96/24TM, DTS-ESTM Discrete 6.1, DTS-ESTM Matrix 6.1 -- AACTM Multichannel 5.1 -- SRS(R) CS2(R) and TSXT(R) -- THX(R) Ultra2TM, THX(R) ReEQTM -- Crossbar Mixer, Signal Generator -- Advanced Post-Processor including: 7.1 Bass Manager, Tone Control, 11- Band Parametric EQ, Delay, 1:2 Upsampler -- Microsoft(R) HDCD(R) -- Thomson MP3 Surround, DTS:Neo6TM, DSD-to-PCM Conversion, Neural Surround, Cirrus Original MultiChannel Surround 2 (COMS2), and more. Please contact your local FAE for more information on available applications. Up to 12 Channels of 32-bit Serial Audio Input
The CS4970X4 DSP family is an enhanced version of the CS4953x DSP family with higher overall performance. In addition to all the mainstream audio processing codes in onchip ROM that the CS4953x DSP offers, the CS4970X4 device family also supports the decoding of major high-definition audio formats. Additionally, the CS4970X4, a dual-core device, performs the high-definition audio decoding on the first core, leaving the second core available for audio post-processing and audio enhancement. The CS4970X4 device will support the most demanding audio post processing requirements. It is also designed as an easy upgrade path to systems currently using the CS495xx or CS4953x device with minor hardware and software changes. Ordering Information See page 30 for ordering information.
Serial Control 1 12 Ch. Audio In / 6 Ch. SACD In
Serial Control 2
Parallel Control
UART
GPIO
Debug
STC 32-bit DSP A D M A Y P 32-bit DSP B X Y TMR1 TMR2
S/PDIF
S/PDIF
P
X
16 Ch PCM Audio Out Ext. Memory Controller PLL
Preliminary Product Information
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2008 Cirrus Logic SEP `08 DS752PP7
http://www.cirrus.com
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
Table of Contents
1. Documentation Strategy ................................................................................................................ 4 2. Overview .......................................................................................................................................... 4
2.1 Migrating from the CS495xx(2) to the CS4970X4 ........................................................................................... 6 2.2 Licensing ......................................................................................................................................................... 6
3. Code Overlays ................................................................................................................................. 6 4. Hardware Functional Description ................................................................................................. 7
4.1 DSP Core ........................................................................................................................................................ 7 4.1.1 DSP Memory ...................................................................................................................................... 7 4.1.2 DMA Controller ................................................................................................................................... 7 4.2 On-chip DSP Peripherals ................................................................................................................................ 7 4.2.1 Digital Audio Input Port (DAI) ............................................................................................................. 7 4.2.2 Digital Audio Output Port (DAO) ........................................................................................................ 8 4.2.3 Serial Control Port 1 & 2 (I2C(R) or SPITM) ............................................................................................ 8 4.2.4 Parallel Control Port ........................................................................................................................... 8 4.2.5 External Memory Interface ................................................................................................................. 8 4.2.6 GPIO .................................................................................................................................................. 8 4.2.7 PLL-based Clock Generator ............................................................................................................... 8 4.3 DSP I/O Description ........................................................................................................................................ 8 4.3.1 Multiplexed Pins ................................................................................................................................. 8 4.3.2 Termination Requirements ................................................................................................................. 8 4.3.3 Pads ................................................................................................................................................... 9 4.4 Application Code Security ............................................................................................................................... 9
5. Characteristics and Specifications ............................................................................................. 10
5.1 Absolute Maximum Ratings .......................................................................................................................... 10 5.2 Recommended Operating Conditions ........................................................................................................... 10 5.3 Digital DC Characteristics ............................................................................................................................. 10 5.4 Power Supply Characteristics ........................................................................................................................11 5.5 Thermal Data (144-Pin LQFP) .......................................................................................................................11 5.6 Switching Characteristics-- RESET ............................................................................................................. 12 5.7 Switching Characteristics -- XTI .................................................................................................................. 12 5.8 Switching Characteristics -- Internal Clock .................................................................................................. 13 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode .............................................................. 13 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode .......................................................... 14 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode ............................................................. 15 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode .......................................................... 16 5.13 Switching Characteristics -- Parallel Control Port - Intel Slave Mode ........................................................ 17 5.14 Switching Characteristics -- Parallel Control Port - Motorola Slave Mode ................................................ 19 5.15 Switching Characteristics -- UART ............................................................................................................ 21 5.16 Switching Characteristics -- Digital Audio Slave Input Port ....................................................................... 22 5.17 Switching Characteristics -- Direct Stream Digital Slave Input Port ........................................................... 23 5.18 Switching Characteristics -- Digital Audio Output Port ............................................................................... 24 5.19 Switching Characteristics -- SDRAM Interface .......................................................................................... 25
6. Ordering Information .................................................................................................................... 30 7. Environmental, Manufacturing, and Handling Information ..................................................... 30 8. Device Pin-Out Diagram ............................................................................................................... 31
8.1 128-Pin LQFP Pin-Out Diagram ................................................................................................................... 31 8.2 144-Pin LQFP Pin-Out Diagram .................................................................................................................. 32
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
9. Package Mechanical Drawings ....................................................................................................33
9.1 128-Pin LQFP Package Drawing ..................................................................................................................33 9.2 144-Pin LQFP Package Drawing ..................................................................................................................34
10. Revision History ..........................................................................................................................35
List of Figures
Figure 1. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 2. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 3. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 4. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 5. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 6. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 7. Parallel Control Port - Intel(R) Mode Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 8. Parallel Control Port - Intel Mode Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 9. Parallel Control Port - Motorola(R) Mode Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 11. UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 12. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 13. Direct Stream Digital - Serial Audio Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 14. Digital Audio Port Timing Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 15. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 16. External Memory Interface - SDRAM Burst Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 17. External Memory Interface - SDRAM Burst Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 18. External Memory Interface - SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 19. External Memory Interface - SDRAM Load Mode Register Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 20. 128-Pin LQFP Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 21. 144-Pin LQFP Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 22. 128-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 23. 144-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of Tables
Table 1. CS4970X4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. CS4970X4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
1. Documentation Strategy
The CS4970X4 data sheet describes the CS4970X4 family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4970X4 family of processors.
Table 1. CS4970X4 Related Documentation Document Name CS4970X4 Data Sheet Description This document A new consolidated documentation set that includes: * Detailed system design information including Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, Etc. Also describes use of DSP Condenser tool. * Detailed firmware design information including signal processing flow diagrams and control API information
CS4970X4 System Designer's Guide
The scope of the CS4970X4 Data Sheet is primarily the hardware specifications of the CS4970X4 family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS4970X4 Data Sheet is the system PCB designer, MCU programmer, and the quality control engineer.
2. Overview
The CS4970X4 DSP Family, together with Cirrus Logic's comprehensive library of audio processing algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a broad array of digital interface products, audio converters, and ARM(R) Processors to meet your audio system-level design requirements. The CS4970X4 is available in 144-pin and 128-pin LQFP packages. The audio processing features of the CS4970X4 product family are a superset of audio features available in the CS4953xx product family. Please refer to Table 2 on page 5 for the speed and firmware features of CS4970X4 product family.
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Table 2. Device and Firmware Selection Guide
Device PreProcess Decode Processor A1 Stereo PCM Multi-Channel PCM
(2:1 Down-sampling Option)
Mid-processor A1
Mid-processor B1
Post-processor1
Dolby PLIIx SRS(R) Circle Surround(R) II
(Stereo In)
APP
(Advanced Post-processing)
CS497004
300 MIPS
Lip Sync Delay
CS497024
300 MIPS
Dolby Digital AAC MP3 HDCD Dolby Digital Plus Dolby True-HD DTS-HD DSD to PCM Conversion
Cirrus Original Multi-Channel Surround (Effects / Reverb Processor) DTS Neo6 Crossbar (Down-mix / Upmix)
(Simultaneous Process)
Dolby Headphone Dolby Virtual Speaker
-Tone Control -Re-EQ -PEQ (up to 11 Bands) -Delay -7.1 Bass Manager -Audio Manager 1:2 Up-sampling
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1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
2.1 Migrating from the CS495xx(2) to the CS4970X4
The CS4970X4 was designed to provide an easy upgrade path from the CS495xx & CS4953x. Although 144-pin versions of the two devices are virtually identical with respect to external system connection, there are some small differences the hardware designer should be aware of: * The PLL supply voltage on the CS4970X4 is 3.3V vs. 1.8V on the CS495xx. * The PLL filter topology is simpler when using the CS4970X4 rather than the CS495xx. * The CS4970X4 adds support for 6-channel DSD input. * The CS4970X4 adds support for TDM mode on both audio input and output ports. * The CS4970X4 does not support external SRAM operation. * The CS4970X4 external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the CS495xx. Some firmware modules also support a 75 MHz CS4970X4 SDRAM bus speed. Please refer to AN304 for details. * The CS4970X4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.
2.2 Licensing
Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the application notes. Please contact your local Cirrus Sales representative for more information.
3. Code Overlays
The suite of software available for the CS4970X4 family consists of operating systems (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Postprocessors. All software components are defined the following list: * OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc. * Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3(R), DTS, PCM, etc. All the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data via I2Sor LJ-formatted digital audio to the CS4970X4 from A/D converters, SPDIF Rx, HDMI Rx, etc. * Mid-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (n 2 channels) or Matrix Decoding (2 n channels). Examples are Dolby ProLogic IIx and DTS Neo:6. * Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Mid-Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, mid-, and post-processors do not need to be reloaded -- only the new decoder (the same is true for the other overlays).
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
4. Hardware Functional Description
4.1 DSP Core
The CS4970X4 is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a highperformance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS4970X4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS4970X4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio decoder and post-processor modules which are available from Cirrus Logic. The CS4970X4 is suitable for Audio Decoder, Audio Post-processor, Audio Encoder, DVD Audio/Video Player, and Digital Broadcast Decoder applications. 4.1.1 DSP Memory Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory for any of today's popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD Master Audio. The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS4970X4 DSP Memory Sizes
Memory Type DSP A DSP B
X Y P
16k SRAM, 32k ROM 24k SRAM, 32k ROM 8k SRAM, 32k ROM
10k SRAM, 8k ROM 16k SRAM, 16k ROM 8k SRAM, 24k ROM
4.1.2 DMA Controller The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI) The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and internally converted to PCM before processing. Additionally support is provided for audio data input to the DSP via the DAI from an HDMI receiver.
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz SPDIF transmitter (data with embedded clock on a single line). 4.2.3 Serial Control Port 1 & 2 (I2C(R) or SPITM) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. 4.2.4 Parallel Control Port The CS4970X4 parallel port supports both Motorola(R) and Intel(R) interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package. 4.2.5 External Memory Interface The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. 4.2.6 GPIO Many of the CS4970X4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.2.7 PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4970X4 defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins Many of the CS4970X4 pins are multi-functional. For details on pin functionality please refer to the CS4970X4 System Designer's Guide. 4.3.2 Termination Requirements Open-drain pins on the CS4970X4 must be pulled high for proper operation. Please refer to the CS4970X4 System Designer's Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper operation.
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
Mode select pins on the CS4970X4 are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4970X4 System Designer's Guide. 4.3.3 Pads The CS4970X4 I/O operate from the 3.3 V supply and are 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5. Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet
typical parameters are measured under the following conditions: T = 25 C, CL = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDDIO| Symbol VDD VDDA VDDIO Iin Vfilt Vinio Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -65 Max 2.0 3.6 3.6 0.3 +/- 10 3.6 5.0 150 Unit V V V V mA V V C
Input pin current, any pin except supplies Input voltage on PLL_REF_RES Input voltage on I/O pins Storage temperature
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDDIO| Commercial Grade (CQZ/CVZ) Symbol VDD VDDA VDDIO TA 0 +25 + 70 C Min 1.71 3.13 3.13 Typ 1.8 3.3 3.3 0 Max 1.89 3.46 3.46 Unit V V V V
Ambient operating temperature
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.) Parameter High-level input voltage Low-level input voltage, except XTI Low-level input voltage, XTI Input Hysteresis High-level output voltage (IO = -4mA), except XTI, SDRAM pins Low-level output voltage (IO = 4mA), except XTI, SDRAM pins SDRAM High-level output voltage (IO = -8mA) SDRAM Low-level output voltage (IO = 8mA) Input leakage current (all digital pins with internal pullup resistors disabled) Symbol VIH VIL VILXTI Vhys VOH VOL VOH VOL IIN VDDIO * 0.9 VDDIO * 0.9 Min 2.0 Typ 0.4 VDDIO * 0.1 VDDIO * 0.1 5 Max 0.8 0.6 Unit V V V V V V V V A
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Parameter Input leakage current (all digital pins with internal pullup resistors enabled, and XTI)
Symbol IIN-PU
Min -
Typ -
Max 50
Unit A
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.) Parameter Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO
1.Dependent on application firmware and DSP clock speed.
Min -
Typ 500 3.5 120
Max -
Unit mA mA mA
5.5 Thermal Data (144-Pin LQFP)
Parameter Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 Symbol Min Typ 48 40 .39 .33 Max C / Watt Unit C / Watt
ja jt
Notes: 1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top
and bottom layers. 2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top and bottom layers and 0.5-oz copper covering 90% of the internal power plane and ground plane layers. 3.To calculate the die temperature for a given power dissipation j = Ambient Temperature + [ (Power Dissipation in Watts) * ja ] 4.To calculate the case temperature for a given power dissipation c = j - [ (Power Dissipation in Watts) * jt ]
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.6 Switching Characteristics-- RESET
Parameter RESET# minimum pulse width low All bidirectional pins high-Z after RESET# low Configuration pins setup before RESET# high Configuration pins hold after RESET# high Symbol Trstl Trst2z Trstsu Trsthld Min 1 50 20 Max 100 Unit s ns ns ns
RESET#
HS[3:0] All Bidirectional Pins Trst2z Trstl
Trstsu Trsthld
Figure 1. RESET Timing
5.7 Switching Characteristics -- XTI
Parameter External Crystal operating frequency1 XTI period XTI high time XTI low time External Crystal Load Capacitance (parallel resonant)2 External Crystal Equivalent Series Resistance Symbol Fxtal Tclki Tclkih Tclkil CL ESR Min 11.2896 33.3 13.3 13.3 10 Max 27 100 18 50 Unit MHz ns ns ns pF W
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, and 27 MHz. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer's recommendation for load capacitor selection.
XTI
t clkih Tclki
Figure 2. XTI Timing
12 Copyright 2008 Cirrus Logic DS752PP7
t clkil
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.8 Switching Characteristics -- Internal Clock
Parameter Internal DCLK frequency1 CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR Internal DCLK period1 CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR DCLKP 6.7 1/Fxtal Symbol Fdclk Fxtal 150 Min Max Unit MHz
ns
1.After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset.
5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode
.
Parameter SCP_CLK frequency1 SCP_CS# falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time SCP_MOSI input SCP_CLK low to SCP_MISO output valid SCP_CLK falling to SCP_IRQ# rising SCP_CS# rising to SCP_IRQ# falling SCP_CLK low to SCP_CS# rising SCP_CS# rising to SCP_MISO output high-Z SCP_CLK rising to SCP_BSY# falling Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspiirqh tspiirql tspicsh tspicsdz tspicbsyl Min 24 20 20 5 5 0 24 20 3*DCLKP+20 Typical Max 25 11 20 Units MHz ns ns ns ns ns ns ns ns ns ns ns
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.At boot the maximum speed is Fxtal/3.
DS752PP7
Copyright 2008 Cirrus Logic
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
tspicss
SCP_CS#
tspickl 0 1 2 6 7 0 5 6 7 tspicsh
SCP_CLK
fspisck tspickh A6 tspidsu tspidh tspidov MSB tspiirqh LSB tspiirql tspicsdz A5 A0 R/W MSB LSB
SCP_MOSI
SCP_MISO
SCP_IRQ#
tspibsyl
SCP_BSY#
Figure 3. Serial Control Port - SPI Slave Mode Timing
5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode
Parameter SCP_CLK frequency1 Symbol fspisck tspicss tspickl tspickh tspidsu tspidh tspidov tspicsl tspicsh tspicsx tspidz Min 18 18 11 5 7 11*DCLKP + (SCP_CLK PERIOD)/2 3*DCLKP 11*DCLKP + (SCP_CLK PERIOD)/2 Typical Max Fxtal/2 (See Footnote 2) 11 20 Units MHz ns ns ns ns ns ns ns ns ns ns
SCP_CS# falling to SCP_CLK rising 3 SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI output valid SCP_CLK low to SCP_CS# falling SCP_CLK low to SCP_CS# rising Bus free time between active SCP_CS# SCP_CLK falling to SCP_MOSI output high-Z
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
.
tspicsx tspicss
EE_CS#
tspicsl tspickl 0 1 2 6 7 0 5 6 7 tspicsh
SCP_CLK
fspisck tspickh A6 tspidsu tspidh tspidov MSB LSB tspidz A5 A0 R/W MSB LSB
SCP_MISO
SCP_MOSI
Figure 4. Serial Control Port - SPI Master Mode Timing
5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode
Parameter SCP_CLK frequency1 SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid SCP_CLK falling to SCP_IRQ# rising NAK condition to SCP_IRQ# low SCP_CLK rising to SCB_BSY# low Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov tiicirqh tiicirql tiicbsyl Min 1.25 1.25 1.25 1.25 2.5 3 100 20 3*DCLKP + 20 3*DCLKP + 20 18 3*DCLKP + 40 Typical Max 400 Units kHz s s s s s s ns ns ns ns ns ns
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.
DS752PP7
Copyright 2008 Cirrus Logic
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
tiicckcmd 0 1
tiicckl 6
tiicr 7 8
tiicf 0 1 6 7 8
tiicckcmd
SCP_CLK
tiicstscl tiicckh A6 A0 tiicdov R/W ACK MSB tiicirqh tiicsu tiich fiicck LSB ACK tiicirql tiicstp tiicbft
SCP_SDA
SCP_IRQ#
tiiccbsyl
SCP_BSY#
Figure 5. Serial Control Port - I2C Slave Mode Timing
5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode
Parameter SCP_CLK frequency SCP_CLK low time SCP_CLK high time SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition START condition to SCP_CLK falling SCP_CLK falling to STOP condition Bus free time between STOP and START conditions Setup time SCP_SDA input valid to SCP_CLK rising Hold time SCP_SDA input after SCP_CLK falling SCP_CLK low to SCP_SDA out valid
1
Symbol fiicck tiicckl tiicckh tiicckcmd tiicstscl tiicstp tiicbft tiicsu tiich tiicdov
Min 1.25 1.25 1.25 1.25 2.5 3 100 20 -
Max 400 -
Units kHz s s s
18
s s s ns ns ns
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application.
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
tiicckcmd 0 1
tiicckl 6
tiicr 7 8
tiicf 0 1 6 7 8
tiicckcmd
SCP_CLK
tiicstscl tiicckh A6 A0 tiicdov R/W ACK MSB fiicck LSB ACK tiicstp tiicbft
SCP_SDA
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
5.13 Switching Characteristics -- Parallel Control Port - Intel Slave Mode
Parameter Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# low Address hold time after PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# high Read Delay between PCP_RD# then PCP_CS# low or PCP_CS# then PCP_RD# low Data valid after PCP_CS# and PCP_RD# low PCP_CS# and PCP_RD# low for read Data hold time after PCP_CS# or PCP_RD# high Data high-Z after PCP_CS# or PCP_RD# high PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for next read1 PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for next write1 PCP_RD# rising to PCP_IRQ# rising Write Delay between PCP_WR# then PCP_CS# low or PCP_CS# then PCP_WR# low Data setup before PCP_CS# or PCP_WR# high PCP_CS# and PCP_WR# low for write Data hold after PCP_CS# or PCP_WR# high PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for next read1 PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for next write1 PCP_WR# rising to PCP_BSY# falling
DS752PP7
Symbol tias tiah
Min 5 5
Typical
Max -
Unit ns ns
ticdr tidd tirpw tidhr tidis tird tirdtw tirdirqhl ticdw tidsu tiwpw tidhw tiwtrd tiwd tiwrbsyl
0 24 8 30 30 0 8 24 8 30 30 2*DCLKP + 20
18 18 12 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Copyright 2008 Cirrus Logic
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
1.The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. CS4970X4 System Designer's Guide should be consulted for the firmware speed limitations.
P C P _ A [3 :0 ] t iah P C P _ D [7 :0 ] PCP_CS# t ic dr PC P _W R # PC P _R D # t ird irq h P C P _ IR Q # t irp w t ias t id d
LSP MSP
t id hr t idis t ird t irdtw
Figure 7. Parallel Control Port - Intel Mode Read Cycle
P C P _A [3:0]
t iah
P C P _D [7:0] P C P _C S #
t ias
LS P
MSP
t id hw t id su t iw p w t iw d t iw trd
t icdw
P C P _R D # P C P _W R #
t iw rb syl P C P _B S Y #
Figure 8. Parallel Control Port - Intel Mode Write Cycle
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.14 Switching Characteristics -- Parallel Control Port - Motorola Slave Mode
Parameter Address setup before PCP_CS# and PCP_DS# low Address hold time after PCP_CS# and PCP_DS# low Read Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high PCP_CS# and PCP_DS# low for read Data hold time after PCP_CS# or PCP_DS# high after read Data high-Z after PCP_CS# or PCP_DS# high after read PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next read1 PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 PCP_RW# rising to PCP_IRQ# falling Write Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data setup before PCP_CS# or PCP_DS# high PCP_CS# and PCP_DS# low for write PCP_R/W# setup before PCP_CS# AND PCP_DS# low PCP_R/W# hold time after PCP_CS# or PCP_DS# high Data hold after PCP_CS# or PCP_DS# high PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with PCP_R/W# high for next read1 PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 PCP_RW# rising to PCP_BSY# falling tmcdw tmdsu tmwpw tmrwsu tmrwhld tmdhw tmwtrd tmwd tmrwbsyl 0 8 24 24 8 8 30 30 2*DCLKP + 20 ns ns ns ns ns ns ns ns ns tmcdr tmdd tmrpw tmdhr tmdis tmrd tmrdtw tmrwirqh 0 24 8 30 30 19 18 12 ns ns ns ns ns ns ns ns Symbol tmas tmah Min 5 5 Max Unit ns ns
1.The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. CS4970X4 System Designer's Guide should be consulted for the firmware speed limitations.
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Copyright 2008 Cirrus Logic
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
H A D D R[3:0]
t m as
H D A TA[7:0] HEN H R /W HDS
t m ah
LS P MSP
t m dhr t m dd t m rw su t m cd r t m rp w t m rd t m dis t m rd tw t m rw hld
t m rw irqh HREQ
Figure 9. Parallel Control Port - Motorola Mode Read Cycle Timing
H A D D R [3 :0 ] t m as
H D A T A [7 :0 ] HEN
tm ah LSP t m dsu t m cdw t m dh w t m w pw
MSP
t m r w h ld tmwd
t m rw irq l
H R /W
t m rw s u
HDS HREQ
t m w trd
Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.15 Switching Characteristics -- UART
Parameter UART_CLK period1 UART_CLK duty cycle Setup time for UART_RXD Hold time for UART_RXD Delay from CLK transition to TXD transition Symbol tuclki tuckrxsu tuckrxdv tucktxdv ttxen ttxhz Min 266 40 5 5 TBD TBD Max 60 29 TBD TBD ns ns ns ns Unit ns %
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
UART_CLK tucktxdv ttxen UART_TXD tuckrxsu UART_RXD UART_TX_EN tuckrxdv ttxhz
Figure 11. UART Timing
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.16 Switching Characteristics -- Digital Audio Slave Input Port
Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn Symbol Tdaiclkp tdaidsu tdaidh Min 40 45 10 5 Max 55 Unit ns % ns ns
DAI_SC LK t daidsu DAI_DATAn t daidh
Figure 12. Digital Audio Input (DAI) Port Timing Diagram
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.17 Switching Characteristics -- Direct Stream Digital Slave Input Port
Parameter DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs DSD_SCLK rising to DSD_A or DSD_B hold time tsdh Min 78 78 1.024 2.048 20 20 Typ Max 3.2 6.4 Unit ns ns MHz MHz ns ns
t dpm
DSD_SCLK (128Fs) DSD_SCLK (64Fs)
t dpm
DSD_A DSD_B ,
Figure 13. Direct Stream Digital - Serial Audio Input Timing
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Copyright 2008 Cirrus Logic
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
5.18 Switching Characteristics -- Digital Audio Output Port
Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode1
1,2
Symbol Tdaomclk Tdaosclk tdaomsck tdaomstlr tdaomlrts tdaomdv
Min 40 45 40 40 -
Max 55 60 19 8 8 10
Unit ns % ns % ns ns ns ns
DAO_SCLK duty cycle for Master or Slave mode1 Master Mode (Output A1 Mode) DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO_SCLK delay from DAO_LRCLK transition, respectively DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 Slave Mode (Output A0 Mode)4 DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 DAO_LRCLK delay from DAO_SCLK transition, respectively3 DAO_SCLK delay from DAO_LRCLK transition, respectively3
3
tdaosdv tdaosstlr tdaoslrts
-
15 30 15
ns ns ns
1.Master mode timing specifications are characterized, not production tested. 2.Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk DAO_MCLK tdaomsck DAO_SCLK tdaomdv DAOn_DATAn tdaomlrts DAO_LRCLK
DAO_LRCLK DAOn_DATAn DAO_SCLK DAO_MCLK
tdaomclk
tdaomsck
tdaomstlr
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 14. Digital Audio Port Timing Master Mode
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
tdaosclk tdaosstlr DAO_LRCLK DAO_LRCLK DAO_SCLK DAO_SCLK tdaosclk DAOn_DATAn tdaosdv tdaoslrts
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 15. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.19 Switching Characteristics -- SDRAM Interface
Refer to Figure 16 through Figure 19.
(SD_CLKOUT = SD_CLKIN) Parameter SD_CLKIN high time SD_CLKIN low time SD_CLKOUT rise/fall time SD_CLKOUT Frequency SD_CLKOUT duty cycle SD_CLKOUT rising edge to signal valid Signal hold from SD_CLKOUT rising edge SD_CLKOUT rising edge to SD_DQMn valid SD_DQMn hold from SD_CLKOUT rising edge SD_DATA valid setup to SD_CLKIN rising edge SD_DATA valid hold to SD_CLKIN rising edge SD_CLKOUT rising edge to ADDRn valid tsdcmdv tsdcmdh tsddqv tsddqh tsddsu tsddh tsdav 1.38 1.3 1.38 3.8 45 1.1 3.8 Symbol tsdclkh tsdclkl tsdclkrf Min 2.3 2.3 150 55 3.8 Typical Max 1 Unit ns ns ns MHz % ns ns ns ns ns ns ns
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Copyright 2008 Cirrus Logic
25
DS752PP7
SD_CLKOUT
t
SD_CS#
t
sdcmdv
sdcmdh
t
sdclkrf
SD_RAS#
SD_CAS#
SD_WE#
tsddqv 00
tsddqh 11
Copyright 2008 Cirrus Logic 26
SD_DQMn
SD_An
tsdcmdv
CAS=2 SD_Dn
tsddsu
tsddh
LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
SD_CLKIN
tsdclkl
tsdclkh
Figure 16. External Memory Interface - SDRAM Burst Read Cycle
DS752PP7 Copyright 2008 Cirrus Logic 27
SD_CLKOUT
tsdcmdv
SD_CS#
tsdcmdh
SD_RAS#
SD_CAS#
SD_WE#
tsddqh
SD_DQMn
00
11
SD_An
SD_Dn
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
Figure 17. External Memory Interface - SDRAM Burst Write Cycle
DS752PP7 Copyright 2008 Cirrus Logic 28
SD_CLKOUT
tsdcmdv SD_CS
tsdcmdv
tsdcmdh
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
SD_DATAn
Figure 18. External Memory Interface - SDRAM Auto Refresh Cycle
DS752PP7 Copyright 2008 Cirrus Logic 29
SD_CLKOUT
tsdcmdv SD_CS
tsdcmdh
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
OPCODE
SD_DATAn
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
Figure 19. External Memory Interface - SDRAM Load Mode Register Cycle
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
6. Ordering Information
The CS4970X4 family part number is described as follows:
CS497NNI-XYZ
where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free
Table 4. Ordering Information
Part No. Grade Temp. Range Container Package
CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR
Commercial Commercial Commercial Commercial
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
Tray 144-pin LQFP Reel Tray 128-pin LQFP Reel
Note: Please contact the factory for availability of the -D (automotive grade) package.
7. Environmental, Manufacturing, and Handling Information
Table 5. Environmental, Manufacturing, & Handling Information
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR
260 C 260 C 260 C 260 C
3 3 3 3
7 Days 7 Days 7 Days 7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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DS752PP7
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
8. Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
GPIO37, SCP1_BSY#, PCP_BSY# GPIO34, SCP1__MISO / SDA
GPIO33, SCP1_MOSI
GPIO35, SCP1_CLK
SD_BA1, EXT_A14
SD_BA0, EXT_A13
110 SD_CS#
RESET#
GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO10, PCP_A2 / A10, SCP2_MOSI GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GPIO7, SCP1_CS#, IOWAIT GPIO6, PCP_CS#, SCP2_CS# VDDIO7 GNDIO7
1
105 GNDIO5
120 VDDIO6
115 GND5
125 VDD6
SD_A10, EXT_A10
EXT_CS1#
SD_RAS#
SD_CAS#
EXT_OE#
EXT_A19
EXT_A18
EXT_A17
EXT_A16
EXT_A15
SD_WE#
GNDIO6
GND6
VDD5
SD_A0, EXT_A0 SD_A1, EXT_A1 100 VDDIO5 SD_A2, EXT_A2
5
GND4 SD_A3, EXT_A3 SD_A4, EXT_A4 95 VDD4 EXT_CS2# SD_A5, EXT_A5 GNDIO4 SD_A6, EXT_A6 90 SD_A7, EXT_A7 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 GND3 85 SD_A11, EXT_A11
GPIO3, DDAC 10 GPIO2, UART_TXD VDD7 GPIO1, UART_RXD GPIO0, UART_CLK, EE_CS# GND7 15 XTAL_OUT XTI XTO GNDA PLL_REF_RES 20 VDDA (3.3V) VDD8 GPIO14, DAI1_DATA3, TM3, DSD3 GPIO13, DAI1_DATA2, TM2, DSD2 GND8 25 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 VDDIO8 DAI1_SCLK, DSD-CLK DAI1_LRCLK, DSD4 30 GNDIO8 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# GPIO43, BDI_CLK, DAI2_SCLK BDI_DATA, DAI2_DATA, DSD5 GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN 35 DBDA DBCK GPIO20, DAO2_DATA2 DAO_MCLK 40 GND1 45 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA VDDIO1 50 VDD2 55 SD_D5, EXT_D5 60
CS497xx4
128-Pin LQFP
SD_A12, EXT_A12 VDD3 SD_CLKEN SD_CLKIN 80 SD_CLKOUT SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 GNDIO3 75 SD_D10, EXT_D10 SD_D11, EXT_D11 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 70 SD_D14, EXT_D14 SD_D15, EXT_D15 SD_D0, EXT_D0 GNDIO2 EXT_WE# 65 SD_D1, EXT_D1
GPIO22, DAO2_SCLK
GPIO16, DAO1_DATA2, HS2
GPIO15, DAO1_DATA1, HS1
DAO1_DATA0, HS0
DAO1_LRCLK
DAO1_SCLK
TEST
VDD1
SD_DQM0
SD_D7, EXT_D7
SD_D6, EXT_D6
SD_D4, EXT_D4
SD_D3, EXT_D3
GPIO19, DAO2_DATA1, HS4
GPIO18, DAO2_DATA0, HS3
Figure 20. 128-Pin LQFP Pin-Out Diagram
DS752PP7 Copyright 2008 Cirrus Logic 31
SD_D2, EXT_D2
GNDIO1
VDDIO2
GND2
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
8.2 144-Pin LQFP Pin-Out Diagram
105 GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO10, PCP_A2 / A10, SCP2_MOSI
108 GPIO41, PCP_IRQ#, SCP2_IRQ#
GPIO37, SCP1_BSY#, PCP_BSY#
GPIO39, PCP_CS#, SCP2_CS#
GPIO34, SCP1__MISO / SDA
GPIO32, SCP1_CS#, IOWAIT
GPIO40, PCP_RD# / RW#
100 GPOI36, SCP1_IRQ#
95 GPIO33, SCP1_MOSI
GPIO35, SCP1_CLK
75 SD_BA0, EXT_A13
SD_BA1, EXT_A14
90 EXT_CS1#
80 SD_RAS#
85 EXT_A17
SD_CAS#
EXT_OE#
EXT_A19
EXT_A18
EXT_A16
EXT_A15
94 GNDIO6
SD_WE#
76 GNDIO5
RESET#
SD_CS#
SD_A10, EXT_A10
GPIO30, XMTB_IN
101 GND6
GPIO9, PCP_A1 / A9 109 GPIO8, PCP_A0 / A8 110 GPIO7, PCP_AD7 / D7 GPIO6, PCP_AD6 / D6 VDDIO7 113 GPIO5, PCP_AD5 / D5 GPIO4, PCP_AD4 / D4 115 GNDIO7 116 GPIO3, PCP_AD3 / D3 GPIO2, PCP_AD2 / D2 VDD7 119 GPIO1, PCP_AD1 / D1 120 GPIO0, PCP_AD0 / D0 GND7 122 XTAL_OUT XTI XTO 125 GNDA 126 NC PLL_REF_RES VDDA (3.3V) 129 VDD8 130 GPIO14, DAI1_DATA3, TM3, DSD3 GPIO13, DAI1_DATA2, TM2, DSD2 GND8 133 GPIO12, DAI1_DATA1, TM1, DSD1 DAI1_DATA0, TM0, DSD0 135 VDDIO8 136 DAI1_SCLK, DSD-CLK DAI1_LRCLK, DSD4 GNDIO8 139 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# 140 GPIO43, BDI_CLK, DAI2_SCLK BDI_DATA, DAI2_DATA, DSD5 GPIO27 GPIO26 144 10 13 15 18 21 24 25 27 30 33 35 GPIO21, DAO2_DATA3 / XMTB, UART_TX_ENABLE 5 GNDIO2 36 1 9
73 VDDIO5 72 SD_A0, EXT_A0 SD_A1, EXT_A1 70 SD_A2, EXT_A2 69 GND4 SD_A3, EXT_A3 SD_A4, EXT_A4 66 VDD4 65 EXT_CS2# SD_A5, EXT_A5 63 GNDIO4 SD_A6, EXT_A6 SD_A7, EXT_A7 60 VDDIO4 SD_A8, EXT_A8 SD_A9, EXT_A9 57 GND3 SD_A11, EXT_A11 55 SD_A12, EXT_A12 54 VDD3 SD_CLKEN SD_CLKIN SD_CLKOUT 50 SD_DQM1 SD_D8, EXT_D8 SD_D9, EXT_D9 47 GNDIO3 SD_D10, EXT_D10 45 SD_D11, EXT_D11 44 VDDIO3 SD_D12, EXT_D12 SD_D13, EXT_D13 SD_D14, EXT_D14 40 SD_D15, EXT_D15 SD_D0, EXT_D0 EXT_WE# 37 SD_D1, EXT_D1
91 VDDIO6
86 GND5
98 VDD6
CS497xx4
144-Pin LQFP
GPIO20, DAO2_DATA2
GPIO28, DDAC
GPIO29, XMTA_IN
DBDA
DBCK
VDD1
GPIO22, DAO2_SCLK
GPIO23, DAO2_LRCLK
GPIO17, DAO1_DATA3 / XMTA
TEST
GPIO18, DAO2_DATA0, HS3
GPIO16, DAO1_DATA2, HS2
GPIO15, DAO1_DATA1, HS1
GPIO19, DAO2_DATA1, HS4
DAO1_DATA0, HS0
DAO_MCLK
DAO1_SCLK
DAO1_LRCLK
GPIO25, UART_TXD, EE_CS#
GND1
VDDIO1
VDD2
83 VDD5
GND2
SD_DQM0 SD_D7, EXT_D7
VDDIO2
GPIO31, UART_CLK
Figure 21. 144-Pin LQFP Pin-Out Diagram
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Copyright 2008 Cirrus Logic
GPIO24, UART_RXD
SD_D2, EXT_D2
GNDIO1
SD_D6, EXT_D6
SD_D5, EXT_D5
SD_D4, EXT_D4
SD_D3, EXT_D3
DS752PP7
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
9. Package Mechanical Drawings
9.1 128-Pin LQFP Package Drawing
D D1
E E1
1 e A1 L
b A
Figure 22. 128-Pin LQFP Package Drawing
Table 6. 128-Pin LQFP Package Characteristics MILLIMETERS DIM MIN NOM MAX MIN NOM MAX INCHES
A A1 b D D1 E E1 e q L L1 ddd
--0.05 0.17
0 0.45
----0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF 0.08
1.60 0.15 0.27
--.002" .007"
7 0.75
0 .018"
----.009" .866" .787" .630" .551" .020" 3.5 .024" .039" REF .003"
.063" .006" .011"
7 .030"
TOLERANCES OF FORM AND POSITION
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
9.2 144-Pin LQFP Package Drawing
E E1
D D1
Notes: Controlling dimension is millimeter. Dimensioning and tolerancing per ASME Y14.5M-1994.
e b
SEATING PLANE ddd M B
B
L1 A A1
L
Figure 23. 144-Pin LQFP Package Drawing
Table 7. 144-Pin LQFP Package Characteristics MILLIMETERS DIM MIN NOM MAX MIN NOM MAX INCHES
A A1 b D D1 E E1 e q L L1 ddd
--0.05 0.17
0 0.45
----0.22 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC --0.60 1.00 REF 0.08
1.60 0.15 0.27
--.002" .007"
7 0.75
0 .018"
----.009" .866" .787" .866" .787" .020" --.024" .039" REF .003"
.063" .006" .011"
7 .030"
TOLERANCES OF FORM AND POSITION
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Copyright 2008 Cirrus Logic
DS752PP7
CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
10. Revision History
Revision A1 PP1 PP2 Date FEB 2007 MAY 2007 JULY 2007 Advance Release. Removed Advanced Product watermark, corrected logo, and added "Preliminary Product Information" on first page and modified legal information to reflect Preliminary Product status. Added notice about status of DTS-HD license on page 1 and 7. Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This applies to both SPI ports. Removed DTS-HD license notice inserted in version PP2. The license for the DTS-HD decoder is now in place.Updated Pin Assignments in 144-Pin LQFP Pin-Out Diagram, removing EE_CS from Pin 7 and adding EE_CS to Pin 25. Updated DAO timing specifications and timing diagrams. Changed product naming conventions in Table 4 and Table 5. Changed references to CS4970X4 Hardware User's Manual to CS4970X4 System Designer's Guide. Changed references to CS4970X4 Firmware User's Manual to CS4970X4 System Designer's Guide Added 128-Pin LQFP Pin-Out and Package drawings. Changed part numbering in Section 6.and Section 7. Added device and firmware selection guide in Table 2. Added typical crystal frequency values in Table Footnote 1 and the Max and Min values of Fxtal in Section 5.7. Removed DSD Phase Modulation Mode from Section 5.17. Removed reference to MCLK in Section 5.17. Redefined Master mode clock speed for SCP_CLK in Section 5.10.. Redefined DC leakage characterization data in Section 5.3, correcting units of measurement. Modified Footnote 1 under Section 5.9. Changed product family numbering from CS497xx to CS4970X4. Corrected product listings in table under Section 5.8 "Switching Characteristics -- Internal Clock" on page 13. Changes
PP3
OCT 2007
PP4
December 20, 2007
PP5 PP6
May 28, 2008 August 4, 2008
PP7
September 30, 2008 Removed references to External Parallel Flash / SRAM Interface.
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Copyright 2008 Cirrus Logic
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CS4970X4 Data Sheet 32-bit High Definition Audio Decoder DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, Pro Logic, AC-3, and Surround EX are registered trademarks of Dolby Laboratories, Inc. AAC is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. DTS and DTS Digital Surround are registered trademarks of the Digital Theater Systems, Inc. DTS Neo:6, DTS-ES 96/24, DTS-ES, DTS 6.1, and DTS 96/24 are trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. THX Technology by Lucasarts Entertainment Company Corporation. THX is a registered trademark of Lucasarts Entertainment Company Corporation. Re-equalization and Ultra 2 are trademarks of Lucasfilm Ltd. SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND(R) TECHNOLOGY (i.e., CIRCLE SURROUND(R) LICENSEES) must first sign a license to purchase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to cslicense@srslabs.com. SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND(R) TECHNOLOGY must carry the Circle Surround(R) logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle Surround logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle Surround(R) products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be used or distributed without a license from Microsoft Licensing, Inc. , HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://www.mp3licensing.com. Motorola and SPI are trademarks of Motorola, Inc. Intel is a registered trademark of Intel Corporation. I2C is a registered trademark of Philips Semiconductor. ARM is a registered trademark of ARM Limited. Logic7 is a registered trademark of Harmon International Industries, Inc.
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Copyright 2008 Cirrus Logic
DS752PP7

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